The increasing demand for consumer electronics, such as digital cameras, MP3 players, laptop computers, and personal data assistants (PDAs), requires non-volatile memory devices to store large amounts of data. Non-volatile memory devices for mass storage are cost driven in order to obtain the lowest cost productions. One type of low cost non-volatile memory is a nitride read only memory (NROM).
A NROM memory cell includes an oxide-nitride-oxide (ONO) gate dielectric and a controlling gate above the ONO gate dielectric. It allows two spatially-separated charge distributions in the nitride layer of the ONO gate dielectric, respectively, at the areas above the source and drain junctions of the memory cell. As a result, the ONO dielectric can store two bits of information per memory cell above those junctions. Thus, the NROM 2-bit memory cell architecture is attractive at least because it can decrease memory array size and the cost of making non-volatile memory devices.
An NROM memory cell can be programmed by “channel hot-electron injection.” In a program operation, depending on the voltages applied to source, drain, and gate nodes, the electrons in the drain's pinch-off region can move toward the nitride layer of the ONO dielectric to program the memory cell. The NROM memory cell can be erased by “band-to-band hot hole injection.” In an erase operation, depending on the voltages applied, holes are generated by band-to-band tunneling under the ONO dielectric of the appropriate junction. The holes can be injected into the ONO dielectric if a strong lateral electric field is generated in the channel region. Those injected holes can combine with electrons of the stored charge to erase the memory cell for a particular bit above a desired junction.
Erase operations rely heavily on having a strong lateral electric field generated in the channel region. To perform an erase operation correctly, proper voltages must be applied to the source, drain, and gate nodes of the memory cell. FIGS. 1 and 2 illustrate prior art NROM cells with the applied node voltages shown to perform prior erase operations. Referring to FIG. 1, a single side erase can be performed using band-to-band hot hole injection for the NROM memory cell. For example, to erase Bit 1, node 101 receives a (−) negative voltage from a negative pump circuit, node 102 receives a (+) positive voltage from a positive pump circuit, and node 103 is connected to ground. To erase Bit 2, node 101 receives a (−) negative voltage from a negative pump circuit, node 102 is connected to ground, and node 103 receives a (+) positive voltage from a positive pump circuit. The following TABLE 1 lists the voltages and connections for the nodes of FIG. 1, as detailed above.
TABLE 1(Prior Erase Operation)NodesErasing Bit 1Erasing Bit 2Node 101(−) Negative Voltage(−) Negative VoltageNode 102(+) Positive VoltageGNDNode 103GND(+) Positive Voltage
This prior NROM memory cell operation suffers from a disadvantage that if the (+) positive voltage applied to nodes 102 or 103 to erase Bit 1 or Bit 2, respectively, exceeds the punch-through voltage of the memory cell, the positive pump circuit will crash, causing the erase operation to fail. This occurs when the bit-line bias is over the punch-through voltage. For example, when a large bias exists between the source and the drain, punch through may occur at the channel region, causing the voltage difference to drop. The drop in the voltage difference may result in an insufficient lateral electric field, thereby impacting an erase operation or causing non-erase of the bit.
Referring to FIG. 2, to erase Bit 1, node 201 receives a (−) negative voltage from a negative pump circuit, node 202 receives a (+) positive voltage from a positive pump circuit, and node 103 is floating. To erase Bit 2, node 201 receives a (−) negative voltage from a negative pump circuit, node 202 is floating, and node 203 receives a (+) positive voltage from a positive pump circuit. The following TABLE 2 lists the voltages and connections for the nodes of FIG. 2, as detailed above.
TABLE 2(Prior Erase Operation)NodesErasing Bit 1Erasing Bit 2Node 201(−) Negative Voltage(−) Negative VoltageNode 202(+) Positive VoltageFloatingNode 203Floating(+) Positive Voltage
This prior NROM memory cell suffers from a disadvantage that nodes 202 or 203, when floating to erase Bits 1 or 2, may be coupled to an uncertain voltage level due to bit-line coupling or leakage current, causing the erase operation to fail. In particular, the uncertainty in voltage level may cause erase non-uniformity across memory cells.
Furthermore, some memory cells in the prior art NORM memory arrays may suffer marginal defects, such as buried drain oxide breakdown, source-drain leakage, and so forth. Such marginal defects can cause serious problems in an NROM memory array after fabrication, and screening such defects during testing can be difficult. As noted above, if one side of a memory cell is connected to GND and the other side of the memory cell is connected to a positive pump circuit, the bit-line bias may exceed the punch-through voltage, causing the pump circuit to crash. Moreover, if one side of the memory cell is floating during an erase, the memory cell can be coupled to an uncertain voltage that causes instabilities during erase operations. For example, the threshold voltage (Vt) distribution after an erase operation will become wider. The variation of the uncertain voltage level may cause erase non-uniformity across the memory cells.
Thus, what is needed are improved NROM non-volatile memory devices and NROM memory cell operations and testing methods to screen for marginal defects.